1. Field of the Invention
Embodiments of the present invention relates to a semiconductor device, and particularly to a semiconductor device in which a front-end section having an interface function and a back-end section having a memory core are integrated on different semiconductor chips.
2. Description of Related Art
The storage capacity required for a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) has been increasing year after year. In order to meet such a demand, a memory device called a multi-chip package in which a plurality of memory chips are stacked has been proposed in recent years. However, each of the memory chips included in the multi-chip package has a so-called frontend section which interfaces with the outside (a memory controller, for example) because each of the memory chips itself is a usual memory chip which operates alone. Therefore, the occupied area allocatable to a memory core in each of the memory chips is limited to the area which is obtained by subtracting the occupied area for the frontend section from the total area. It is thus difficult to increase the storage capacity per a memory chip substantially.
Furthermore, there is a problem that it is difficult to speedup transistors constituting the frontend section because the frontend section and the backend section including the memory core are produced simultaneously despite the circuits constituting the frontend section belong to a so-called logic circuits.
As a solution to such problems, a method to configure a semiconductor device by integrating the frontend section and the backend section in separate chips and stacking the chips is proposed. According to the method, as for a core chip which is integrated with the backend section, it becomes possible to increase the storage capacity per a chip (per a core chip) because the occupied area allocatable to the memory core increases. At the same time, as for an interface chip which is integrated with the frontend section, it becomes possible to configure the circuits with fast transistors because it can be produced by a process different from those for the core chip. In addition, because it is also possible to allocate a plurality of core chips to an interface chip, it becomes possible to offer a high-speed semiconductor device with a very large-capacity as a whole.
As for such a semiconductor device, Japanese Patent Application Laid-Open No. 2011-081731 discloses a technique for securing a sufficient temporal margin (latch margin) for a process in which the interface chip captures read data. According to the technique, in a core chip, a replica circuit of a circuit pertaining to outputting of read data, and an output timing adjustment circuit that controls an output timing of read data are provided. In an interface chip, a process monitor circuit containing a variable delay circuit is provided. The process monitor circuit adjusts an amount of delay by the variable delay circuit in such a way that it becomes equal to an amount of delay in the replica circuit and reflect the result in the output timing adjustment circuit. By adjusting the timing of when each of the core chips outputs read data in that manner, it becomes possible to secure a sufficient latch margin for a process in which the interface chip captures read data.
In a semiconductor device of a type that uses an interface chip, for example, when a writing operation is performed, write data is input to the interface chip from an external controller via a data input/output terminal. The interface chip generates a control signal (referred to as a “second control signal”, hereinafter) based on a write command, and outputs the write data to a core chip at a timing determined by the second control signal. Meanwhile, the core chip also generates a control signal (referred to as a “first control signal”, hereinafter) based on the write command, and receives the write data from the interface chip at a timing determined by the first control signal.
The write data is transmitted to each core chip by the mechanism described above. Therefore, the first control signal needs to be synchronized with the second control signal. If there is a certain amount or more of deviation from the state of synchronization, the writing operation cannot be properly performed. An acceptable range of deviation from the state of synchronization is referred to as a “timing margin”.
A configuration has been previously developed for ensuring the first and second control signals are synchronized. This configuration can deal with both the situation where the first control signal advances ahead of the second control signal and the situation where the first control signal is delayed relative to the second control signal. In the former case, a delay adjustment circuit is provided between a circuit (write control timing adjustment circuit) that generates the first control signal, and a circuit (command generation circuit) that generates an internal command inside the core chip. The delay adjustment circuit is a circuit that delays a timing at which an internal write command generated by the command generation circuit is supplied to the write control timing adjustment circuit. The larger the amount of delay by the delay adjustment circuit becomes, the more the generation timing of the first control signal is delayed. An amount of delay that should be set in the delay adjustment circuit is measured through attempts of writing operation in production-process tests, and the amount is then set in the delay adjustment circuit.
In the case of the configuration, one possible problem is that a write recovery time tWR (or a period of time from when an inputting of write data to the data input/output terminal is completed to when it becomes possible to input a precharge command) becomes longer. That is, the operation speed of the semiconductor device varies according to temperature. The amount of advancement of the first control signal relative to the second control signal varies according to temperature, too. Therefore, in order to support all temperatures, the amount of delay is inevitably set based on a temperature at which the amount of advancement of the first control signal relative to the second control signal is maximized. Ideally speaking, a process by the core chip of capturing the write data (or a process of capturing at a timing determined by the first control signal) should be carried out immediately after the write data is output from the interface chip at a timing determined by the second control signal. However, as a result of setting the amount of delay as described above, depending on temperature, there might be a time lag between the outputting of the write data (from the interface chip) and the capturing (by the core chip) of the write data. Consequently, the write recovery time becomes longer.
The above description is true of a reading operation. In the case of the reading operation, one possible problem is that an address access time tAA (or a period of time from when an inputting of a column address to an address terminal is started to when an outputting of the read data from the data input/output terminal is completed) becomes longer.
That is, the problem with the configuration is that, in the reading and the writing operation, an optimal amount of delay acquired when the temperature is low is not optimal when the temperature is high (and vice versa).